That new moniker is in keeping with a rebranded sibling of the p5 servers, the eServer i5s, which made their debut in early May as kickers to the iSeries line of OS/400 servers. A name change is supposed to be indicative of a substantial change in a given technology, and while a lot of marketeers in IT overuse this tactic of separating old and new products, in this case a lot of neat technologies that have been lacking in the pSeries Unix servers are now there.
What the press releases will not say is that those technologies debuted several years ago in the iSeries line, which is also based on the Power chips and their associated chassis. To be blunt about the situation, the eServer p5 is what happens when you prop AIX up off the Power iron so it can run on an iSeries server rigged out with pSeries I/O and with its sophisticated dynamic, logical partitioning.
Since 1997, the AS/400 and RS/6000 midrange server lines have been based on a common core hardware platform, and over time the hardware in these lines have converged considerably. The iSeries and pSeries machines that debuted in late 2000 still used different memory addressing schemes and I/O subsystems, which is necessary to support the very different OS/400 and AIX operating systems.
The way that IBM describes it, the Apache, Northstar, S-Star, Power4, and Power5 frames bear some resemblance to the Boeing 747. There are two versions – a decked out machine designed with integrated systems for carrying passengers, their luggage, and providing facilities and a beverage service (this is the OS/400 flavor), and a bare-bones system using the same frame, engines, and flight systems, but giving carriers the option and responsibility of adding their own components to it for freight hauling or military use (this is the AIX version).
The i in iSeries and i5 stands for integration, and everything you need to do data processing is included with these machines, from the operating system, database, middleware, compilers, and so forth. The p in pSeries and p5 stands for performance and price/performance, and this is what IBM is really selling into the Unix space. The oomph of the 64-bit PowerPC and Power chips and very aggressive bang for the buck are, in fact, the main weapons that what have allowed IBM to become a contender in the Unix market in the past five years.
The Unix market is a three-horse race between Hewlett-Packard and Sun Microsystems, who have long dominated the field, and IBM, the Unix wannabe that hesitantly entered the market in 1989 and only caught Unix religion when it became apparent in the dot-com bubble that Sun was growing at 50% a year and that if IBM didn’t build and deliver excellent Unix servers, Sun would set the pace in the server market, not IBM.
As we all know, the dot-com bubble burst, severely wounding Sun and giving IBM an opportunity to hit it hard with its Power-based machines. IBM has also been able to attack HP and Compaq as the two merged and transitioned away from its AlphaServer/Tru64 Unix and PA-RISC/HP-UX lines toward a unified box running HP-UX on Itanium-based Integrity servers (which also support Linux and Windows). Sun’s financial woes and its difficulties in delivering its UltraSparc processors and servers to market plus the HP-Compaq merger and the transition of its two Unix lines gave IBM a chance to eat market share with very fast Power4 and Power4+ servers running AIX and Linux, and eat it did. Soon, this will be harder for Big Blue to do.
But not quite yet. Sun is still getting its act together in creating Opteron processors for entry and midrange servers, and while it has smartly partnered with Fujitsu to deliver an integrated Sparc platform in late 2005 or early 2006, that is a long time away in the computer business. The HP-Compaq merger has been accomplished (somewhat bumpily from a technical and economic perspective, but more smoothly than anyone would have hoped or guessed) and HP is readying its own single Unix for PA-RISC and Itanium for the second half of 2005 (HP-UX 11i v3, as that version is called, was initially expected by the end of 2004). So for the next year, IBM is going to try to use the Squadron servers with Power5 and Power5+ processors to try to gain a few more vital points of market share. It has better than even odds of doing this, based on past history.
IBM’s rivals, Sun and HP, will probably counter that the Power5 is just more of the same Power4, with expected improvements in processor and server technology, tweaks in AIX software, and logical partitioning capabilities stolen from the iSeries. (The so-called micropartitioning of the Virtualization Engine hypervisor created for the Squadrons allows up to 10 logical partitions to be created per Power5 processor core on a Squadron box.) Well, that’s exactly what the Power5 machines are, and quite frankly, that is all IBM and its customers need them to be–provided that IBM chops prices, too.
The Power5 processor is the third dual-core chip that Big Blue has delivered to the market, and it is a whopper at 389 square millimeters and 276 million transistors. It is made using a 130 nanometer copper/SOI process that allows IBM to run the Power5 cores at 1.5 GHz, 1.65 GHz, and 1.9 GHz, which is exactly the planned clock speed range IBM set two years ago, and put 1.9MB of on-chip L2 cache for the two cores to share. The Power4 from nearly three years ago was 415 square millimeters and was made in a 180 nanometer process that only packed 170 million transistors on the chip; it ran at 1 GHz, 1.1 GHz, and 1.3 GHz; the Power4+ that launched last year was made in the 130 nanometer copper/SOI process, boosted on-chip L2 cache from 1.41MB to 1.5 MB, and cranked up the clock speed to 1.2 GHz, 1.45 GHz, 1.7 GHz, and 1.9 GHz.
Mark Papermaster is vice president for technology development for IBM’s Systems Group, which means he is the person who is in charge of the Power chip and chipsets used to create the servers and workstations that use those chips. He says that there are a lot of other features in the Power5 chips and their machines that make them fast. The Power5 uses a modified Power4 core that has simultaneous multithreading (what Intel calls hyperthreading) added in.
SMT boosts the performance of a processor by making it look like two virtual processors to an operating system. (The S-Star PowerPC processors had hyperthreading, but the Power4s did not.) Papermaster says that IBM’s implementation of SMT is yielding better results than it expected, with somewhere between 30% to 40% performance increase (depending on workload) compared to a Power4 chip without SMT and running at the same clock speed. The Power5 chips also have the main memory controller on the chip, and IBM has optimized the data paths through L1, L2, and L3 caches.
Papermaster says that IBM is still putting together a portfolio of benchmarks to describe the new eServer p5 servers that use the Power5 processors, but that generally speaking, the machines offer twice the performance as the current Power4 or Power4+ pSeries servers that they replace. On tests that are more sensitive to memory bandwidth, I/O bandwidth, or number crunching capacity (such as TPC-C or Linpack), the Squadron boxes are doing a little better than this, but on integer performance, it is a little bit lower. What IBM focused on with the Squadron design was approaching the mythical near-linear scalability–add one processor, get one more processor’s worth of work done–that all server vendors are shooting for.
IBM is launching four different eServer p5 Squadron boxes today, and they are a bit different from the i5 Squadrons announced in May, but nonetheless based on the same core designs.
The p5-520 is the entry two-way box, which has a single Power5 chip with two cores running at 1.65GHz. It has 36MB of L3 cache and offers from 1GB to 32GB of main memory. The 520 has a 4U chassis that has enough room for four disk drives; Ultra320 SCSI drives with 36 GB, 73 GB, or 147GB capacities are supported. The machine has a dual-port Ultra320 SCSI controller with an optional RAID 5 daughter card for customers who want extra protection.
The machine also has six PCI-X I/O slots, two Gigabit Ethernet NICs and a Hardware Management Console (HMC) slot for plugging in the outboard Linux box that runs the logical partitions on all Squadron machines. The i5 variants of the Squadrons all support OS/400 V5R3, AIX 5.2 and 5.3, and 64-bit Linuxes from Red Hat and Novell; the p5 machines will support AIX 5.2 and 5.3 as well as Linux across their line, but will only support OS/400 on the bigger p5-570 machines. The p5-520 can be bought as a deskside machine or a rack-mounted machine. A base machine, presumably with 1GB of main memory, no disk, and a single 1.65GHz processor, has a list price of $12,190.
The p5-550 is the machine that IBM would not even bother to launch were it not for the fact that Oracle only allows its Oracle 10g Standard Edition database to run on machines that cannot physically have any more than four processors. Oracle 10g Standard Edition costs $15,000 per processor, which is a lot less than the $40,000 list price for the Enterprise Edition. The entry Oracle 10g Standard Edition One (SEO), which can only be put on machines with one or two processors, costs $4,995 per processor.
Oracle drives the Unix market, and its pricing practices drive at least some of the engineering in the Unix server market. The p5-550 supports two 1.65GHz Power5 chips on two system boards with a minimum of one core activated on each system board. Each system board has 36MB of L3 cache and can support up to 32GB of main memory. This machine also fits in a 4U chassis with four drive bays, like the p5-520, but it only has five PCI-X slots. It has dual Gigabit NICs and the HMC as well. It can support up to eight I/O towers for a total of 15.2TB of disk capacity and 60 PCI-X slots. The base p5-550, presumably with two 1.65GHz cores activated, 2GB of main memory, and no disk, has a list price of $22,100.
The p5-570 has the clustering electronics in the box that allow up to four of the four-way Squadron chassis to be linked together into a single system image. (IBM says that this is true SMP technology, not NUMA clustering. But it is probably a hybrid of SMP and NUMA. This is exactly how IBM build the Summit xSeries servers, which use Intel’s Xeon MP and Itanium 2 processors, and it is how the i5 Model 570 was created, too.)
IBM has two different flavors of the p5-570. The p5-570 Express configuration uses a slower 1.5GHz Power5 core, and can only expand up to 8-way processing (four processors in two chassis). IBM is no doubt getting much higher yields on the slower Power5 processors, which explains why IBM wants to steer customers into using them. This is probably also why the 1.5GHz chips are also being used heavily in the i5 line, where performance is not as important to customers–at least according to IBM. (iSeries customers would probably argue with this sentiment, but what can be honestly said is that the p5, which has to compete in the aggressive Unix market, needs the fastest chips IBM can supply.)
The p5-570 Express comes with 2, 4, or 8 of those 1.5GHz Power5 cores activated and supports from 2GB to 256GB of 266MHz DDR1 main memory. This machine consists of two 4U chassis that mount in a rack; the servers can link to up to a dozen I/O expansion drawers. Each p5-570 chassis (whether it is the plain vanilla box or the 570 Express box) has six drive bays, dual Ultra320 SCSI controllers, dual Gigabit NICs, and redundant, hot-plug power and fans. A base p5-570 Express will have a list price of $28,659; it is unclear what is in this configuration, but considering that it costs more than a vanilla p5-570, it has to include extra stuff.
Finally, that plain vanilla p5-570 uses 1.65GHz or 1.9GHz Power5 processors in a NUMA system that spans from 2 to 16 processors and from one to four 4U chassis. This box can span from 2GB to 256GB of main memory using 266MHz DDR1 memory. If customers want faster memory performance with their 1.9GHz Power5 chips, they can buy from 4GB to 64GB of 533MHz DDR2 main memory. Each two-core chip module has its own 36MB L3 cache. The vanilla p5-570 box supports up to 20 I/O drawers. A base p5-570 (non-Express) costs $25,928.
IBM had originally planned to get the AIX 5.3 release out the door late last year, but getting AIX extracted from the Power iron and onto the hypervisor has apparently proved to be a challenge. The Squadron boxes, which will be available on August 31, are a few months behind unofficial launch dates in the rumor mill from last year. The eServer i5 got the Power5 processors first mainly and simply because OS/400 already had a hypervisor layer–in fact, if IBM had been able to manufacture a Squadron server in December, the company could have probably launched the i5s back then.
Because AIX 5.3 is such a different technology and probably has a very small number of applications certified for it, Big Blue has taken the unusual step of supporting AIX 5.2 on the Squadron boxes in addition to supporting the new AIX 5.3. However, the Virtual Engine hypervisor will only allow AIX 5.2 partition granularity to be as fine as a single Power5 processor core. To get the new logical partitioning that supports up to 10 micropartitions per core, customers have to use AIX 5.3.
