Richardson, Texas-based chip producer Cyrix Corp is going after the market for 80486 notebook CPUs with the announcement today of its first 80486 socket compatible processor the Cx486S2/50, the first in a family of 80486SX and DX pin-out products; and the Cx486SLC/e, an enhanced version of the 16-bit Cx486SLC launched earlier this year. It intends, quite simply to overtake Intel in the pin-out sector by 1993 with the Cx486S2/50. The Cx486SLC/e it believes will come to dominate the entry-level notebook market, providing the basis for machines that can outperform current 80386SL-based models for prices below $2,000. Cyrix anticipates that the volume market in 1993 and 1994 will be dominated by pin-outs and is already preparing a roadmap of future offerings. Scheduled for the first quarter of 1993 is a high performance 80486SX device, codenamed M6n, which will offer power saving features like System Management Mode, static 3.3V operation and suspend-resume with 20 MIPS performance and 50MHz clock speeds. The current offering, the Cx486S2/50 – Cyrix’s fourth new product this year – is an 80486SX socket compatible processor offering 50MHz speed and an on-chip write-back cache, FasCache, which the company says provides a faster performance than Intel’s 33Mhz 80486SX. FasCache incorporates write-back technology, increased write buffers and burst write capability. It reduces bus traffic by cacheing writes in addition to words and only sending writes to the external memory when they are needed. Reduced congestion means the Cx486S2/50 stalls less than other clock-doubled CPUs, the company claims. In support of the write-back cache, the new processor doubles the number of write buffers and supports burst writes. This, in combination with the FasCache can reduce bus congestion by up to 98%. The processor implements a 80486SX instruction set with single-cycle execution unit, 32-bit internal data path and on-chip hardware integer multiplier coupled to an internal 2Kb write-back cache.
Larger FasCache and higher clock speeds External interface is provided through a 32-bit 80486 burst mode bus that can burst read and write. The Cx486S2/50 will be sampling this quarter and shipping in volume in the first quarter of 1993. It costs $250 for 1,000-up, which is nearly half that of Intel’s 50MHz 80486DX2 at $490. A separate surface-mount floating point unit that works in conjunction with the new CPU costs $35 for 1,000-up. The next 80486DX socket-compatible processor, the M7, is based on the Cx486S2/50 but offers a larger FasCache and higher clock speeds. The new Cx486SLC/e, running at 25MHz and 33MHz, offers System Management Mode – a flexible memory address space of up to 32Mb that imposes less CPU overhead and cuts power consumption by 25% in addition to the features of the conventional Cx486SLC. Cx486SLC/e-based notebooks will bring about a dramatic improvement on those available today, Cyrix reckons, being 30% smaller, under 5 lbs in weight and more energy efficient. And to stimulate the process, it has been busy collaborating with other companies in order to develop systems for Cx486SLC/e notebooks. Western Digital Corp’s WD7855 system controller supports the System Management facility, cache utilisation and 3.3V operation; Phoenix Technologies Ltd’s power management system, PhoenixMiser helps reduce power consumption; and VLSI Technologies Inc’s Scamp II chip set also supports the Cyrix Management Mode to improve battery life. The Cx486SL/e is sampling today with volume shipments set for December. The 25MHz 5V version is $75 for 1,000-up; the 25MHz 3.3V is $90 and the 33MHz 5V is $100. It is packaged in a 100-lead PQFP package. A companion maths co-processor, the Cx487SLC/e is also available, packaged in an 80-lead PQFP. The predecessor Cx486SLC is to be phased out in January.
