IBM will describe a technique for laying down Silicon circuits on a layer of non-conducting Silicon Dioxide laid on the standard Silicon wafer on which chips are built up, at the annual semiconductor conference in San Francisco this week: the technique is said to lead to a three-fold improvement in the speed of CMOS circuits by ensuring that current travels by the shortest route and not through the foundation Silicon, and reducing the damage that can be done by stray radiation picked up in the substrate; IBM says the technique is application to other processes as well as CMOS.
