Among the implementation advances highlighted by IBM in the Summit models of ES/9000 is a switch to logic chips that include 2.5nS access, 8nS cycle time static RAM arrays integrated on the same chip.
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The Summit models support up to 1Gb of central memory and up to 8Gb of expanded memory, double the previous maximum available on the 3090s.
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In performance terms, IBM says that the ES/9000 Model 900 – the six-processor Summit – delivers 1.7 to 1.9 times the processor performance of the 3090 Model 600J in commercial applications; 2.0 to 2.7 times in scalar, and 2.0 to 2.8 times in vector supercomputing performance. i b mAs for the top-end 9370 replacement, the ES/9000 Model 170, IBM says it provides up to 2.4 times the internal commercial performance and up to 4.6 times the internal scientific performance of the 9377 Model 90, while the top-end dual processor 4391, the Model 480 has over 4.0 times internal performance of the 4381-92E in commercial work.
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One of the problems IBM has created with its new numbering schema is that in referring to the new models, one has to keep unravelling it to understand what one is talking about and where it fits in: we’ve found that the table we prepared two weeks ago based on the pre-announcement information is an invaluable guide, and we reprint it below – with the memory and channels added and the errors corrected!
Summary of ES/9000 announcement
Model Processors MIPS(e) Maximum Max Escon, memory std chnnls Summit 9021-900 Six 212 9Gb 256 9021-820 Four 161 9Gb 256
3090 9021-720 Six 112 4.5Gb 128 9021-620 Four 85 4.5Gb 128 9021-580 Three 65 2.25Gb 64 9021-500 Two 45 2.25Gb 64 9021-340 One 24 1.15Gb 64 9021-330 One 20 640Mb 64
4391 9121-480 Two 40 1Gb 48 9121-440 Two 32 1Gb 48 9121-320 One 23 1Gb 48 9121-260 One 16 1Gb 48 9121-210 One 12 1Gb 48 9121-190 One 8 512Mb 32
9370 9221-170 One 6.5 256Mb 24 9221-150 One 5 256Mb 12 9221-130 One 3 256Mb 12 9221-120 One 2 256Mb 12
M i s c e l l a n y
Not mentioned in the table are the confusing 3090-9000T models: these are migration machines that enable users of the old technology 3090-110J, 120J, 170J, 180J and 250J and 120E and S, 150E and S, 170S and 250S to get onto the ES/9000 upgrade path: 110 and 120 users must go to a 15T, 150 users to a 17T or 25T, 180 users to a 25T, and 250S users to a 28T, so that you can’t move onto the upgrade path for the Brave New World without paying for a model that has additional power.
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High-end ES/9000 design increases parallelism, IBM says, by dividing control functions between the system control element and the interconnect communication element: the first serves the processors and central storage, the second handles the data flow for expanded storage and the channel subsystem; each system controller has a data path to and from each communication controlller and contains a second level high cache in addition to each processor’s internal cache to reduce the number of instruction and data fetches from main memory.
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IBM has also designed new large scale function modules pre-tested subassemblies that contains the TCM logic board, power system, and cooling equipment, which rolls easily into place for connection to the system, for installation of add-ons such as Vector Facilities.
The processor controller for the ES/9000 processors is programmed to compile a detailed error history, do much of the analysis, and automatically initiate a maintenance call to IBM’s service network.
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A key development – to make things eaiser for IBM and its engineers as much as anything – is that more function is now in field-replaceable units so that more of the machine cane be swapped at one time: no adaptor boards are needed in either ESCON or conventional block multiplexer channels, because their functions are now incorporated into the TCM logic – so the entire TCM unit is swapped to fix a channel fault in the new regime.
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On some water-cooled ES/9000s – only the Summit models presumably, although IBM does its best to avoid differentiating these from the repackaged 3
090Js, there is a new 256Kb cache split into independent instruction and data caches, so that instruction and data can be fetched on the same CPU cycle.
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In the Summit models, the System Control Elements – successors to the 3092 controller, are linked directly to each processor in the complex rather than simply linked to each other as in the 3090 line.
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The Summit models include replicated arithmetic-logic units so that within each processor, the instruction stream can be split and the separate parts executed in parallel – except when one comes to a branch and holds the whole thing up: Prime Computer Inc and Tandem Computers Inc are companies that have used the concept in the past, but in what we believe is a first, IBM has arranged things so that instructions can be executed in a different order from the one in which they show up in the program; a patented Virtual Register Mmanagement Mechanism keeps watch over this, and puts the stream back into the right sequence after execution; the fact that IBM has had to adopt such a complex approach to improve the throughput suggests that the raw performance of the chips is below what it had been hoping to achieve.
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The channel subsystem consists of one Channel Control Element, which can serve up to 48 traditional or Escon channels, IBM says: the former run at the present 4.5Mbytes-per-second limit, the latter run at up to 10Mbytes-per-second.
