Motorola Inc was irritatingly uninformative in its Tuesday nursery-style spoiler for Intel Corp’s launch of the 80486 (CI No 1,144), but Microbytes Daily managed to get out of the company that the 68040 floating-point unit has 80-bits of precision, with a data format conforming to IEEE Standard 754, with instructions code-compatible with the 68882 floating point chip, and that performance is enhanced because no bus cycles are required to address, load values, and fetch results from an external floating-point chip; a snoop controller is used to maintain cache coherency, particularly in a multiprocessor environment where several processors operate on the same set of data – but Motorola declined to reveal such trivial information as the size of the caches, although a year ago, it was saying they would be 8Kb each; like the 68030, the 68040 has a Harvard-style architecture with separate data and program buses; the internal demand-paged memory management unit is more or less as on the 68030, but apparently implements only a subset of the 68030’s memory manager, and while this should not affect the operation of applications, operating systems that rely on a hardware memory manager to provide memory protection between applications may have to be modified slightly to work with the 68040’s memory management unit.
