The forthcoming Am29000 32-bit reduced instruction set microprocessor – Advanced Micro Devices’ first microprocessor with a native instruction set and its first major part in CMOS (CI Nos 642, 643) will have three separate 32-bit buses – data, instruction and address. The part will be clocked at 25MHz, and will come in a 169-pin package. Being a RISC, it will have a large number – 192 – of on-chip registers, as well as concurrent instruction and data accesses, 4Gb of virtual address space with demand paging, 4Gb address range with paged virtual memory, a 64-entry on-board memory-management unit, and floating-point acceleration. The microprocessor will also include an on-chip branch target cache for single-cycle branching. Advanced Micro hopes to see first silicon on the part in early summer, but claims to have scored several design wins with it on the basis of preliminary information. The Sunnyvale, California company expects it to be used inter alia in embedded controller environments that demand high performance such as robotics, as well as demanding applications such as workstations for foreign-language translation, speech recognition and other machine intelligence systems. A 29000-based Unix co-processor for IBM Personals, and a VME board computer are also likely. The Am29027 floating-point arithmetic accelerator will follow the 29000 within three months, and will consist of a 64-bit arithmetic-logic unit, 64-bit data path, and a control unit; it will implement both single- and double-precision working as well as integer and conversion operations.
