IBM has unveiled a new processor for system-on-chip (SoC) product families in the communication, storage, consumer, and aerospace and defense markets. LSI has collaborated with IBM on the development of the processor core PowerPC 476FP.
LSI intends to use the 476F PowerPC core in its upcoming multicore platform architecture for networking applications. It operates at clock speeds in excess of 1.6 GHz, and 2.5 Dhrystone MIPS per MHz.
The company said that the processor extends the scalability of IBM’s Power Architecture in traditional embedded applications, and provides a growth platform for applications such as 4G networks and WiMax infrastructure products.
According to IBM, the 476FP offering includes an architectural extension of IBM’s CoreConnect local bus technology (PLB6), supporting coherency for multiple processors and providing scalability that is suitable for customers designing families of products and focusing on software re-use.
IBM said that LSI has designed a configurable level 2 (L2) memory cache that is coupled to the processor, which helps the PowerPC 476FP achieve improved performance. There are three configurations of the L2 (256K, 512K and 1M) to allow customer optimisation in a given application.
The 476FP offering consists of the PowerPC 476FP, the Level 2 cache/cache controller, and PLB6, a new architectural extension of the CoreConnect local bus architecture. Collectively, these elements enable SoC designers to develop families of products, scaling the number of processor cores from 1 to 16 on the bus, the company said.
In addition, the bus fabric on the PLB6 is capable of supporting up to eight coherent elements, enabling SoC designers to mix and match I/O masters, processors and other accelerators within the fabric.
Richard Busch, director of ASIC products at IBM, said: We are pleased to announce this new embedded PowerPC processor. Our collaboration with LSI brings together IBM’s expertise in processor development with LSI’s experience in networking and storage architectures, optimising this core to address today’s high-speed embedded requirements.
