Figuring we’d be blinded by science, the way IBM Corp and Motorola Inc announced their Somerset group’s new Mach 5, 0.25 micron PowerPC design process left a bunch of folk – including us – still scratching their heads over some of the finer points (CI No 3,193). For the record, Motorola calls Mach 5 its PPC4 process, IBM calls it CMOS 6X. Both manufacture 250MHz PowerPC 604e microprocessors using this process. Mach 5 improves on Somerset’s existing hybrid 0.25 micron design – used, for example, to manufacture 300MHz PowerPC 603e – by generating less heat and drawing less current. The first G3 PowerPC microarchitecture part due later this summer – code-named Arthur – will use the hybrid 0.25 design, not Mach 5. It’s effectively an enhanced PowerPC 603e design. Observers figure Apple Computer Inc may be able to ship PowerPC 704 (G3) systems by winter time. Somerset’s future G4 design is expected to incorporate as many as four CPUs and a cache in a single processing module (CI No 3,142)
