Microchip Technology, a provider of microcontroller and analog semiconductors, has rolled out ENC624J600 – a new IEEE 802.3 compliant, 100Mbps Ethernet interface controllers. Each controller has a factory-preprogrammed a Media Access Controller (MAC) address and 24 Kbytes of configurable SRAM for packet transmit/receive buffering and data storage.
According to Microchip, the new Ethernet controllers combine a 10/100Base-TX physical interface (PHY) and a MAC with a hardware cryptographic security engine, and can connect to PIC microcontroller through an serial peripheral interface (SPI) or a flexible parallel interface.
The company said that the new Ethernet controllers integrate hardware cryptographic security engines to perform RSA, Diffie-Hellman, MD5 and SHA-1 algorithm computations in support of cryptographic protocols such as SSL/TLS, SSH and various VPNs. These integrated hardware features enable secure data transmissions with reduced code size, enhanced connection establishment and throughput.
In addition, the configurable, 24 Kbyte SRAM buffer memory provides data-management system that supports packet storage, retrieval and modification that reduces memory requirements for the host microcontroller, the Microchip added.
Microchip claims that with an SPI interface, the new Ethernet controllers require only four pins to connect to the microcontroller, enabling the use of smaller MCU packages for space-constrained applications.
Reportedly, the company offers a TCP/IP stack that can be used for free with any of its 8-, 16- or 32-bit PIC microcontrollers or dsPIC digital signal controllers. The stack includes Secure Sockets Layer (SSL) encryption and a TCP/IP configuration wizard for the configuration of Ethernet projects.
