Synopsys and Semiconductor Manufacturing International Corporation (SMIC) have introduced the 65-nanometer (nm) RTL-to-GDSII reference design flow, version 4.0.
The SMIC-Synopsys Reference Flow 4.0, a result of the collaboration between Synopsys Professional Services and SMIC, adds the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology reportedly expanding the resources available to designers to address low power and design-for-manufacturing challenges at smaller process nodes.
The reference design flow utilises Synopsys’ Galaxy Implementation Platform enabling designers to implement low power techniques throughout the design flow including RTL synthesis and test, physical implementation and signoff stages. In addition, IC Compiler’s Zroute technology supports SMIC’s 65-nm routing rules using routing algorithms to evaluate the impact of manufacturing rules and timing.
According to the companies, the integration of Zroute balances design-for-manufacturing (DFM) optimisation techniques with design timing, area, power and signal integrity for a particular chip design.
Additional features of the reference design flow include multi-corner multi-mode (MCMM) optimisation and critical area analysis and reduction, using IC Compiler, and design-for-test (DFT) synthesis combined with on-chip clocking control support for automatic generation of at-speed tests.
Paul Ouyang, vice president of design services Centre at SMIC, said: SMIC’s 65-nanometer logic process requires a flow that addresses critical timing, power leakage and DFM issues to reduce risk and increase the quality of results.
We worked closely with Synopsys to once again deliver a solution that enables our mutual customers to take advantage of both companies’ leading technologies. We look forward to an ongoing relationship with Synopsys as we move toward even more advanced process nodes.
