Denali Software, a provider of electronic design automation (EDA) software and intellectual property (IP), has unveiled a new phase PHY technology for DDR SDRAM physical interfaces, which the company says will offer memory system performance up to 1066MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower.
According to Denali Software, the phase PHY technology applies an oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. The DDR PHY technology is offered as a synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.
The company said that the oversampling architecture employs an 8- or 16-phase lock loop (PLL) and performs pattern matching to determine the correct data sample points for DDR data for each transaction.
By managing the data capture on a per-bit basis, PHY closes timing at 1066MHz clock rates. The differences in the routing of data and data strobe signals are calibrated in the silicon, eliminating the need for hand layout. The fully-synchronous design provides flexibility for floorplanning, pin placement, and power routing and uses EDA toolsets, the company said.
Mike McKeon, director of PHY IP at Denali, said: The continued demand for increased bandwidth in various internet and electronic applications is driving the need for DDR3 technology and for the ability to support data rates up to 2133Mbp/s. Our DDR phase PHY is cutting-edge technology, delivering effective management of GHz clock speeds and a perfect match for our customers’ specific design implementation needs.
