Intel Corp is to describe the P6 iteration of its iAPX-86 architecture at the International Solid State Circuits Conference in San Francisco next week but needless to say, by the time the company comes to deliver the paper, most of the detail will be out – and much of it is out already. The P6, as expected – and long hinted at by Intel – uses a RISC core and takes a similar approach to translating iAPX-86 instructions as to the Advanced Micro Devices Inc K5 and Nexgen Microsystems Inc Nx586. The other key feature of the P6, as reported, is the integrated second level cache – a separate chip, initially of 256Kb capacity, with 512Kb planned, that will be packaged with the CPU on a multi-chip module. The P6, which can issue four instructions per cycle, compared with two for the Pentium, is rated at 250 to 300 MIPS. There will be a high-speed 128-bit bus in between the processor and memory, an Advanced Processor Interrupt Controller for multiprocessing, built-in Level 2 cache controller, and a larger 32Kb Level 1 cache. It implements Dynamic Execution architecture, which supports multiple-branch prediction, so the processor can track numerous branch instructions; data flow analysis, which analyzes code as it comes into the processor to minimise data dependencies; and speculative execution of instructions that might be needed. Intel reportedly looks to ship perhaps 200,000 by year-end and is already shipping engineering samples.
