IBM Corp has so totally mismanaged the campaign to turn the PowerPC RISC into a successful merchant part that most of the wins there have been have been down to Motorola Inc rather than IBM. Motorola cannot afford to wait for IBM and has to behave as far as it is allowed to as if IBM did not exist. And that is precisely what it was doing, last Friday when it announced an innovative vector processing architecture called Vecomp, for Vector Communications Processor. Vecomp, which combines a PowerPC core with a vector processing array, is aimed at the high- performance, low-cost digital processing requirements of wireless communications systems and implements a Single-Instruction, Multiple Data architecture, ideal for signal processing algorithms typical of wireless communications. The Vecomp processors integrate multiple processing elements with the a high-bandwidth input-output subsystem on a single chip. Low-level signal processing code runs on the vector array, and the high- level control functions and operating system run on the PowerPC core. This distribution of the system software enables the vector core to be fully utilized running compute-intensive routines, making the most efficient use of the high processing bandwidth available, says Motorola, which reckons that by replacing multiple processing engines or fixed-function ASICs in the cellular network, the new chip can bring big cost-savings, adding flexibility by making the system software-upgradable instead of requiring an ASIC to be replaced. The first Vecomp is due for introduction in 1997.
